Clock and Data Recovery (CDR) circuits form a critical part of receivers in serializer-deserializer (SerDes) communication channels. The CDR circuits are used to track the phase of a sampling clock based on some criterion like minimizing mean squared-error (MSE). It is important that the CDR circuits operate well enough to achieve a very low target bit-error rate (BER) on the order of 1e-12 or 1e-15. The CDR circuits in common use can be broadly classified into two categories, baud-rate CDR and bang-bang CDR. There are advantages and disadvantages associated with each category.
In bang-bang (or Alexander) type CDR, a received signal is sampled twice every symbol period, also called a unit interval (UI). Ideally one sample is at a crossing boundary and another sample is at a center of a receiver data eye. Two consecutive data samples (V[K−1] and V[K]) and one transition (or crossing) sample (V[K−½]) between the two data samples are used to decide whether a current sampling phase is lagging or leading an ideal sampling point. The sampling phase is then corrected accordingly. In a CDR circuit using a conventional bang-bang phase detector (BBPD), the phase of a transition sampling clock settles at the median of the jitter distribution after convergence.